// R32 cpu test bench
// 28 May 2009

`include "..\..\r3220_def.v"
`timescale 1ns/100ps

module r3220_cpu_test;
	reg clk=0;
	reg clkx2=0;
	reg rst=1;
	reg [3:0] irq_i = 4'b0000;
	reg firq = 0;

	wire [31:0] cpu_data_o;
	wire [31:0] cpu_data_i;
	wire [23:0] cpu_adr_o;
	wire cpu_cyc_o;
	wire cpu_sel_o;
	wire cpu_stb_o;
	wire cpu_we_o;
	wire uart_txd;
	wire [3:0] irq_ack_o;
	wire firq_ack_o;

	always #6.25 clkx2=~clkx2;
	always #12.5 clk=~clk;

// The R3220 cpu module
	r3220_cpu cpu(clk,rst,cpu_adr_o,cpu_data_i,cpu_data_o,cpu_cyc_o,cpu_sel_o,cpu_stb_o,cpu_we_o,cpu_ack_i,irq_i,irq_ack_o,firq,firq_ack_o);
	
	wire [31:0] output0;
	wire [31:0] strobe1;

	wire LTC1650x6_clk_o;
	wire LTC1650x6_do_o;
	wire [4:0] LTC1650x5_cs_o;

	reg ddc_din_i;
	wire ddc_c_clk_o;
	wire ddc_d_clk_o;
	wire ddc_conv_o;
	wire ddc_d_xmit;
	wire ddc_range_o;

	wire spi_sc_clk_i;
	wire spi_sc_cs_i;
	wire spi_sc_data_i;
	wire spi_sc_data_o;

	wire spi_adc_clk_o;
	wire spi_adc_data_o;
	wire spi_adc_data_i;
	wire [1:0] spi_adc_cs_o;
	wire [1:0] spi_adc_in_i;

	wire sdram_cke_o;
	wire sdram_ncs_o;
	wire sdram_nras_o;
	wire sdram_ncas_o;
	wire sdram_nwe_o;
	wire [10:0] sdram_addr_o;
	wire [1:0] sdram_ba_o;
	wire [3:0] sdram_dqm_o;
	wire [31:0] sdram_dq;

	wire [3:0] system_irq_o;
	wire [3:0] system_irq_ack_i;
	wire system_firq_o;
	wire system_firq_ack_i;
	
	wire [2:0] misc_ip_i;
	
	system the_system(
	  clk,
	  clkx2,
	  rst,
	  cpu_adr_o,	
	  cpu_data_o,
  	  cpu_data_i,
	  cpu_cyc_o,
	  cpu_stb_o,
	  cpu_we_o,
	  cpu_ack_i,
	  
	  output0,
	  strobe1,

	  LTC1650x5_clk_o,
	  LTC1650x5_do_o,
	  LTC1650x5_cs_o,

	  ad_sclk_o,
	  ad_nld_o,
	  ad_do,
	  ad_nsync_o,

	  uart_txd,	// rxd - loopback
	  uart_txd,

	  system_irq_o,
	  system_irq_ack_i,
	  system_firq_o,
	  system_firq_ack_i,

	  ddc_din_i,
	  ddc_c_clk_o,
	  ddc_d_clk_o,
	  ddc_conv_o,
	  ddc_d_xmit,
	  ddc_range_o,

	  spi_sc_clk_i,
	  spi_sc_cs_i,
	  spi_sc_data_i,
	  spi_sc_data_o,

	  spi_adc_clk_o,
	  spi_adc_data_o,
	  spi_adc_data_i,
	  spi_adc_cs_o,
	  spi_adc_in_i,

	  misc_ip_i,
	  
          sdram_cke_o,	// SDRAM stuff...
	  sdram_ncs_o,
	  sdram_nras_o,
	  sdram_ncas_o,
 	  sdram_nwe_o,
	  sdram_addr_o,
	  sdram_ba_o,
	  sdram_dqm_o,
  	  sdram_dq
	  );

	assign spi_sc_clk_i = spi_adc_clk_o;
	assign spi_sc_cs_i = spi_adc_cs_o[0];
	assign spi_sc_data_i = spi_adc_data_o;

	assign spi_adc_data_i = spi_sc_data_o;
	
	initial begin
		:local integer i;

		#100 rst = 0;
/*
		#300 irq_i = 4'b0001; 
		#1100 firq = 1;
		#300 irq_i = 4'b0000;
		#400 firq = 0;

		#1000 firq = 1;
		#100 firq = 0;
*/
		// Enable memory reading
		#60000 $stop;
	end	

endmodule

/*
// The system memory for the test bench
// This is deliberatly slowed and the address is latched at the start of the cycle
module system_slow(
	input clk,
	input [23:0] adr_i,	
	input [`DATA_SPAN] dat_i,
	output [`DATA_SPAN] dat_o,
	input cyc_i,
	input stb_i,
	input  we_i,
	output reg ack_o
	);

	reg ram_we;
	wire [`DATA_SPAN] ram_do;
	reg wait1;
	reg wait2;
	reg wait3;
	reg wait4;
	reg [13:0] memaddr;

	ram mem(memaddr,clk,dat_i,ram_we,dat_o);

	always@(*) begin
	  ram_we = cyc_i & stb_i & we_i;	// Write if we have a valid cycle
	  end

	always@(posedge clk) begin
        if ( (cyc_i & stb_i) & ~wait1 & ~wait1 )
	    memaddr <=  adr_i[12:0]; // Latch the address
	  end

	always@(posedge clk) begin
        if ( (cyc_i & stb_i) )
          wait1 <= 1;
	  else
          wait1 <= 0;
	  end

	always@(posedge clk) begin
        if ( (cyc_i & stb_i) & wait1 )
          wait2 <= wait1;
	  else
          wait2 <= 0;
	  end

	always@(posedge clk) begin
        if ( (cyc_i & stb_i) & wait1 & wait2)
          wait3 <= wait2;
	  else
          wait3 <= 0;
	  end

	always@(posedge clk) begin
        if ( (cyc_i & stb_i) & wait1 & wait2 & wait3 )
          wait4 <= wait3;
	  else
          wait4 <= 0;
	  end

	always@(*) begin
        if ( (cyc_i & stb_i) & wait1 & wait2 & wait3 & wait4)
	    ack_o = 1;
	  else
	    ack_o = 0;
	  end
endmodule

// This is fast
module system(
	input clk,
	input [23:0] adr_i,	
	input [`DATA_SPAN] dat_i,
	output [`DATA_SPAN] dat_o,
	input cyc_i,
	input stb_i,
	input  we_i,
	output reg ack_o
	);

	reg [2:0] LEDs;
	reg ram_we;
	wire [`DATA_SPAN] ram_do;

	sram_20 mem(adr_i[13:0],clk,dat_i,ram_we,dat_o);

	assign bCS_Mem = (adr_i[23:14] == 0);
	assign bCS_LED = (adr_i[16] == 1'b1);

	always@(*) begin
	  ram_we = bCS_Mem & cyc_i & stb_i & we_i;	// Write if we have a valid cycle
	  end

	always@(posedge clk) begin
        if ( (cyc_i & stb_i) )
	    ack_o = 1;
	  else
	    ack_o = 0;
	  end

	always@(posedge clk) begin
        if ( bCS_LED &cyc_i & stb_i & we_i )
          LEDs = dat_i[2:0];
	  end

endmodule
*/